Field of the Invention
This invention relates to a digital signal reproducing circuit that is applicable to digital audio disc playback systems, tape-record information playback systems, digital data processing systems, etc., and more particularly, it relates to a circuit for reproducing digital signals, which are encoded according to a predetermined format for a minimum or maximum pulse inversion period, and clock signals from the reproduced or received digital signals.
In recent years, the digital signal reproducing circuit has been used in a variety of digital systems. In such digital systems, the digital signals are modulated, recorded or transmitted by a variety of digital modulation systems. Digital signals modulated by these digital modulation systems are predetermined without failure by their digital modulation systems for a minimum inversion period and maximum inversion period format. A circuit to reproduce correct data and a clock signal from these modulated digital signals includes a data slice section, a phase synchronization loop circuit section and a digital signal reproducing section.
This phase synchronization loop circuit section reproduces the clock signal (PLCK), and the digital signal reproducing section reads out the digital signal from the input digital signal, using this clock signal (PLCK). Below, as an example, the digital signal reproducing circuit will be explained in the context of being used in digital audio disc players.
In the optical disc 11 in FIG. 1 a digital EMF modulated signal, which is from of digital modulation, is recorded. From this optical disc 11 the signal (RF) is read out using a pickup. This signal (RF) is made binary by the wave-shaping circuit 13, and the clock signal (PLCK) and digital signal (DOUT) EFM modulated are reproduced from this binary signal (DRF) by means of the PLL circuit section 14 and digital signal reproducing section 14. Both the clock signal (PLCK) and digital signal (DOUT) are synchronized, and fed to the demodulation circuit, not illustrated.
In FIG. 1, as the signal (RF) read out by the pickup 12 passes through the finite band line, the signal DC level varies in the form of signal drop-out due to flaws; in the optical disc 11 and the low pass component of the signal itself. A similar effect is experienced in a digital data processing system, because the digital data passes through a frequency non-linear area in the system.
The wave-shaping circuit 13 converts this RF signal into the binary signal (DRF). As an example of this wave-shaping circuit there are U.S. Ser. No. 300,604 which issued as U.S. Pat. No. 4,574,206. In addition to these, a variety of wave-shaping circuits are known. However, it is difficult to set in an optimum way the DC reference voltage to produce the binary signal used in this circuit. In case the RF signal is compared with the DC reference voltage that is not the optimum value, the error between the optimum DC reference voltage and the actual DC reference is converted into a phase error. In FIG. 2 is shown the phase relation among binary signals DRF-a, DRF-b and DRF-c obtained when the DC reference voltage varies as a, b and c. The waveform DRF-a indicates the output waveform when the actual DC reference voltage becomes higher than the optimum DC reference voltage. In this output waveform (DRF-a), the leading edge is delayed, and the trailing edge is advanced.
The delay and advance of this leading edge do not exert a bad influence upon the PLCK in the PLL circuit section. Because this delay and advance are erased, the phase error signal to control VCO is not generated. However, there is a defect that there is not sufficient phase margin. In case the actual DC reference voltage is the optimum DC reference voltage (DRF-b), the phases are in order at the trailing edge of PLCK and at the leading edge of DRF-b, and DRF-b is read out at the later leading edge of PLCK. In this state, it is known that the maximum permissible phase margin is of .+-..pi.. On the one hand, in the state of DRF-c, the phase margin of one side only has .pi./2, and in case even if the phase error of more than .pi./2 is produced, a bad influence is exerted upon the reproduction of PLCK.